PhD Candidate · McGill University

Marwan Jalaleddine

I am a doctoral candidate in Electrical Engineering at McGill University. My research concerns decoding algorithms for error-correcting codes, which recover transmitted data corrupted by channel noise, and the hardware architectures that implement them.

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Beirut · 2015 to 2019

Undergraduate studies

I received the Bachelor of Engineering in Electrical and Computer Engineering from the American University of Beirut. These studies established my foundation in engineering problem solving, together with a lasting interest in applying engineering to the public good.

  • BEng, High Distinction
  • American University of Beirut

Montreal · 2019 to 2021

Graduate studies

In 2019 I joined the Integrated Systems for Information Processing Laboratory at McGill University, under the supervision of Prof. Warren J. Gross, to pursue a master's degree.

  • Master's degree
  • GRAND

McGill · 2020 to now

Teaching

Since 2020 I have led the laboratory and tutorial sessions of Computer Organization, Digital Systems and Digital Logic, in which students program in ARM assembly and implement digital circuits on FPGA boards. Across 370 course evaluations, students rated my assistance with the course material at 4.2 out of 5.

Teaching evaluations

PhD · 2021 to 2022

Doctoral studies

I subsequently undertook doctoral studies in order to extend the research begun during my master's degree and to make further contributions to the field.

  • PhD

Montreal · 2026

Prospective positions

I am completing my doctoral studies and am seeking industrial or academic positions, beginning in 2027, in channel coding, decoder hardware and machine learning for communications.

  • Available from 2027
  • Academia
  • Industry
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Interactive tool

Decoder hardware comparator

Published decoder ASIC implementations compiled for this comparator, plotted by throughput and energy per bit. The full comparator additionally provides error-rate curves, technology-node scaling, filters and the complete data table.

Throughput vs. energy efficiency, all designs

Diamonds denote designs with an error-rate curve. Hovering over a point shows its values; clicking it opens the design in the full comparator.

Open the full comparator

Research

Selected papers

  1. Preprint
    A Universal Systematic Method to Generate Error Patterns on Memoryless Channels
    Marwan Jalaleddine, Jiajie Li, Syed Mohsin Abbas, and Warren J Gross
    2026
    Summary PDF
  2. COMML
    Enabling Fast Polar SC Decoding with IR-HARQ
    Marwan Jalaleddine, Mohamad Ali Jarkas, Jiajie Li, and Warren J Gross
    IEEE Communications Letters, 2026
    DOI PDF
  3. ICC
    Hardware-friendly IR-HARQ for Polar SCL Decoders
    Marwan Jalaleddine, Jiajie Li, and Warren J Gross
    In 2025 IEEE International Conference on Communications, 2025
    DOI PDF
  4. ISIT
    Partial Ordered Statistics Decoding with Enhanced Error Patterns
    Marwan Jalaleddine, Huayi Zhou, Jiajie Li, and Warren J Gross
    In IEEE International Symposium on Information Theory, 2023
    DOI PDF
All publications

Recent updates

News

Nov 04, 2025 US patent granted: “Polar decoder and associated method” (US 12,463,747 B2), an optimization-based polar decoder developed with Huayi Zhou, Ryan Seah, and Warren J. Gross.
Jun 01, 2025 Paper accepted at ICC 2025: “Hardware-friendly IR-HARQ for Polar SCL Decoders”
Sep 15, 2024 Published in IEEE TCOMM: “Reduced-Complexity Projection-Aggregation List Decoder for Reed-Muller Codes”
Jul 01, 2024 Published in IEEE JSAC: “Decoding of Polar Codes Using Quadratic Unconstrained Binary Optimization”